Caching Processor General Registers

Author(s):
Robert Yung and Neil C. Wilhelm
Report Number:	Date Published:	Available Formats:
TR-1995-42	June 1995	Portable Document Format (PDF) Request Hard Copy
Abstract
VLlW, multi-context, or windowed-register architectures may require one hundred or more process or registers. It can be difficult to design a register file with so many registers that meets processor cycle time requirements. We propose to resolve this problem by taking advantage of register values that are bypassed within a processor's pipeline, and supplementing the bypassed values with values supplied by a small register cache. If the register cache is sufficiently small, then it can be designed to meet a fast target cycle time. We call this combination of bypassing and register caching the Register Scoreboard and Cache. We develop a simple performance model and show by simulations that it can be effective for windowed-register architectures.

Caching Processor General Registers