A Power-Efficient Network On-Chip Topology
A Power-Efficient Network On-Chip Topology
J. Camacho, J. Duato, J. Flich, H. Eberle, W. Olesinski
01 January 2011
International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, New York, NY, 2011
Venue : N/A