Wafer-Testing of Optoelectronic-Gigascale CMOS Integrated Circuits

Gigascale integrated (GSI) chips with high-bandwidth, integrated optoelectronic (OE) and photonic components are an emerging technology. In this paper, we present the prospects and opportunities for wafer-testing of chips with electrical and optical I/O interconnects. The issues and requirements of testing OE-GSI chips during high-volume manufacturing are identified and discussed. Two probe substrate technologies based on microelectromechanical systems (MEMS) for simultaneously interfacing a multitude of surface-normal optical I/Os and high-density electrical I/Os are detailed. The first probe substrate comprises vertically compliant probes for contacting electrical I/Os and grating-in-waveguide optical probes for optical I/O coupling. The second MEMS probe module uses microsockets and through-substrate vias (TSVs) to contact pillar-shaped electrical and optical I/Os and to redistribute the signals, respectively.