Switched-capacitor (SC) voltage regulators are widely used in on-chip power management, due to the high efficiency at integer-ratio step-down and feasibility of integration. Theoretical analysis and optimization for SC DC-DC converters have been presented in prior works, however optimization of different capacitors, namely flying and input/output decoupling capacitors, in SC voltage regulators (SCVRs) under an area constraint has not been addressed. In this work, we propose a methodology to optimize flying and decoupling capacitance for area-constrained on-chip SCVRs to achieve the highest system-level power efficiency. Considering both conversion efficiency and droop voltage against fast load transients, the proposed model determines the optimal ratio between flying and decoupling capacitance for fixed total area. These models are validated with integrated 2:1 SCVR implementations in both 65nm and 32nm CMOS. Experiments show high model accuracy on efficiency and droop modeling for a broad range of flying and decoupling capacitance. The maximum and average error of the predicted optimal ratio between flying and decoupling capacitance is 5% and 1.7%, respectively.