A Performance Evaluation of 2D-Mesh, Ring, and Crossbar Interconnects for Chip Multi-Processors
A Performance Evaluation of 2D-Mesh, Ring, and Crossbar Interconnects for Chip Multi-Processors
J. Camacho Villanueva, J. Flich, J. Duato, H. Eberle, N. Gura, W. Olesinski
12 December 2009
International Workshop on Network on Chip Architectures (NoCArc'09), New York, NY, Dec 12, 2009
Venue : N/A