Hardware Generation from the Delite Compiler Framework
Stanford University, Department of Electrical Engineering
Oracle Fellowship Recipient
Oracle Principal Investigator
Hassan Chafi, Vice President, Research and Advanced Development
Slowdown of Moore's law and the end of Dennard scaling has forced a radical change in the architectural landscape, requiring computing systems to become increasingly parallel and heterogeneous. Custom accelerators which make use of reconfigurable hardware fabric are a strong contender for continued compute performance improvements, but traditionally require programmers to sacrifice productivity and code versatility for higher performance. Domain-specific languages (DSLs) are a promising alternative that offers both programmability and efficiency. At Stanford, we have developed an extensible compiler framework called Delite that eases the creation and compilation of DSLs, as well as the optimization of applications written in those DSLs. Delite currently generates C++, Scala, and CUDA code for each computation node, simultaneously utilizing heterogeneous compute resources across computations. We are currently adding support for hardware generation so that Delite can also target custom accelerators like FPGAs and ASICs.
Our approach for hardware generation is to first translate the Delite IR into a lower-level hardware representation which contains various parameterizable building blocks for computation and memory. We will then model area, power, and energy using prebuilt IR component models and use these models to explore the hardware design space. We also plan to build tools to estimate various design parameters using our abstract hardware description. Once we can generate hardware, we will look at how to best manage data transfer and communication between the custom accelerator and the host.