BRAVO -- Biased Locking for Reader-Writer Locks
Dave Dice, Alex Kogan, EuroSys 2019 is the primary venue, but we also intend to circulate the idea to various linux mailing lists for discussion about use in the kernel and user-space, and also to the java.util.concurrent community.

Improving Parallelism in Hardware Transactional Memory
Dave Dice, Maurice Herlihy, Alex Kogan, ACM Transactions on Architecture and Code Optimization (TACO)

Malthusian Locks - slides for EuroSys 2017
Dave Dice, EuroSys 2017

Persistent Memory Transactions
Virendra Marathe, Achin Mishra, Amee Trivedi, Yihe Huang, Faisal Zaghloul, Sanidhya Kashyap, Margo Seltzer, Tim Harris, Steve Byan, William Bridge, Dave Dice, USENIX Annual Technical Conference

Dekker's mutual exclusion algorithm made RW-safe.
Peter A. Buhr, David Dice, Wim H. Hesselink, Concurrency and Computation: Practice and Experience (CONCURRENCY) 28(1):144-165 (2016)

Fast non-intrusive memory reclamation for highly-concurrent data structures
Dave Dice, Maurice Herlihy, Alex Kogan, ISMM 2016

Fast non-intrusive memory reclamation for highly-concurrent data structures.
Dave Dice, Maurice Herlihy, Alex Kogan, ISMM

Malthusian Locks
Dave Dice, PPoPP 2017

Primus Inter Pares: Improving Parallelism in Hardware Transactional Memory
Dave Dice, Maurice Herlihy, Alex Kogan, ACM/IEEE International Symposium on Computer Architecture (ISCA)

Refined transactional lock elision
Dave Dice, Alex Kogan, Yossi Lev, PPOPP 2016

Refined transactional lock elision.
Dave Dice, Alex Kogan, Yossi Lev, PPOPP

Evaluating HTM for Pauseless Garbage Collectors in Java.
Maria Carpen Amarie, Dave Dice, Patrick Marlier, Gaël Thomas 0001, Pascal Felber, TrustCom/BigDataSE/ISPA 2015:1-8

High-performance N-thread software solutions for mutual exclusion.
Peter A. Buhr, David Dice, Wim H. Hesselink, Concurrency and Computation: Practice and Experience (CONCURRENCY) 27(3):651-701 (2015)

Lock Cohorting: A General Technique for Designing NUMA Locks.
David Dice, Virendra J. Marathe, Nir Shavit, TOPC 1(2):13 (2015)

Malthusian Locks.
Dave Dice, CoRR abs/1511.06035 (2015)

The Influence of Malloc Placement on TSX Hardware Transactional Memory.
Dave Dice, Tim Harris, Alex Kogan, Yossi Lev, CoRR abs/1504.04640 (2015)

The Influence of Malloc Placement on TSX Hardware Transactional Memory.
Dave Dice, Tim Harris 0001, Alex Kogan, Yossi Lev, CoRR

The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Jons-Tobias Wamhoff, Stephan Diestelhorst, Christoph Fetzer, Patrick Marlier, Pascal Felber, Dave Dice, Software Engineering & Management 2015:141-142

Adaptive Integration of Hardware and Software Lock Elision Techniques.
Dave Dice, Alex Kogan, Yossi Lev, Timothy Merrifield, Mark Moir, SPAA 2014

Adaptive integration of hardware and software lock elision techniques.
Dave Dice, Alex Kogan, Yossi Lev, Timothy Merrifield, Mark Moir, SPAA

Adaptive integration of hardware and software lock elision techniques.
Dave Dice, Alex Kogan, Yossi Lev, Timothy Merrifield, Mark Moir, SPAA 2014:188-197

Brief announcement: persistent unfairness arising from cache residency imbalance.
Dave Dice, Virendra J. Marathe, Nir Shavit, SPAA 2014:82-83

Hardware extensions to make lazy subscription safe
Dave Dice, Tim Harris, Alex Kogan, Yossi Lev, Mark Moir, Extended version of our WTTM 2014 paper.

Hardware extensions to make lazy subscription safe.
Dave Dice, Timothy L. Harris, Alex Kogan, Yossi Lev, Mark Moir, CoRR

Hardware extensions to make lazy subscription safe.
Dave Dice, Timothy L. Harris, Alex Kogan, Yossi Lev, Mark Moir, CoRR abs/1407.6968 (2014)

Pitfalls of lazy subscription
Dave Dice, Tim Harris, Alex Kogan, Yossi Lev, Mark Moir, 6th Workshop on the Theory of Transactional Memory (WTTM 2014)

Software-based contention management for efficient compare-and-swap operations.
Dave Dice, Danny Hendler, Ilya Mirsky, Concurrency and Computation: Practice and Experience (CONCURRENCY) 26(14):2386-2404 (2014)

The TURBO Diaries: Application-controlled Frequency Scaling Explained.
Jons-Tobias Wamhoff, Stephan Diestelhorst, Christof Fetzer, Patrick Marlier, Pascal Felber, Dave Dice, USENIX Annual Technical Conference 2014:193-204

Lightweight Contention Management for Efficient Compare-and-Swap Operations
Dave Dice, Danny Hendler, Ilya Mirsky, CoRR abs/1305.5800 (2013)

Lightweight Contention Management for Efficient Compare-and-Swap Operations.
David Dice, Danny Hendler, Ilya Mirsky, Euro-Par 2013:595-606

Message Passing or Shared Memory - Evaluating the Delegation Abstraction for Multicores.
Irina Calciu, Dave Dice, Tim Harris 0001, Maurice Herlihy, Alex Kogan, Virendra J. Marathe, Mark Moir, OPODIS

Message Passing or Shared Memory - Evaluating the Delegation Abstraction for Multicores.
Irina Calciu, Dave Dice, Tim Harris 0001, Maurice Herlihy, Alex Kogan, Virendra J. Marathe, Mark Moir, PODC

Message Passing or Shared Memory: Evaluating the Delegation Abstraction for Multicores.
Irina Calciu, Dave Dice, Tim Harris, Maurice Herlihy, Alex Kogan, Virendra J. Marathe, Mark Moir, OPODIS 2013:83-97

NUMA-aware reader-writer locks.
Irina Calciu, David Dice, Yossi Lev, Victor Luchangco, Virendra J. Marathe, Nir Shavit, PPOPP 2013:157-166

NUMA-aware reader-writer locks.
Irina Calciu, David Dice, Yossi Lev, Victor Luchangco, Virendra J. Marathe, Nir Shavit, PPOPP

Scalable statistics counters (Poster)
Dave Dice, Yossi Lev, Mark Moir, PPoPP 2013

Scalable statistics counters.
Dave Dice, Yossi Lev, Mark Moir, PPOPP

Scalable statistics counters.
Dave Dice, Yossi Lev, Mark Moir, SPAA 2013:43-52

Scalable statistics counters.
Dave Dice, Yossi Lev, Mark Moir, SPAA

Using hardware transactional memory to correct and simplify and readers-writer lock algorithm.
Dave Dice, Yossi Lev, Yujie Liu, Victor Luchangco, Mark Moir, PPOPP 2013:261-270

Using hardware transactional memory to correct and simplify and readers-writer lock algorithm.
Dave Dice, Yossi Lev, Yujie Liu, Victor Luchangco, Mark Moir, PPOPP

Lock cohorting: a general technique for designing NUMA locks.
David Dice, Virendra Marathe, Nir Shavit, PPOPP 2012:247-256

Brief announcement: a partitioned ticket lock.
David Dice, SPAA 2011:309-310

Brief announcement: multilane - a concurrent blocking multiset.
David Dice, Oleksandr Otenko, SPAA 2011:313-314

Cache index-aware memory allocation.
Yehuda Afek, David Dice, Adam Morrison, ISMM 2011:55-64

Flat-combining NUMA locks.
David Dice, Virendra Marathe, Nir Shavit, SPAA 2011:65-74

Efficient Lock Free Privatization.
Yehuda Afek, Hillel Avni, David Dice, Nir Shavit, OPODIS 2010:333-347

Simplifying concurrent algorithms by exploiting hardware transactional memory.
David Dice, Yossi Lev, Virendra J. Marathe, Mark Moir, Daniel Nussbaum, Marek Olszewski, SPAA

Simplifying concurrent algorithms by exploiting hardware transactional memory.
David Dice, Yossi Lev, Virendra Marathe, Mark Moir, Daniel Nussbaum, Marek Olszewski, SPAA 2010:325-334

TLRW: return of the read-write lock.
David Dice, Nir Shavit, SPAA 2010:284-293

Transactional Mutex Locks.
Luke Dalessandro, David Dice, Michael Scott, Nir Shavit, Michael Spear, Euro-Par 2010:2-13

Early Experience with a Commercial Hardware Transactional Memory Implementation
David Dice, Yossi Lev, Mark Moir, Daniel Nussbaum, Marek Olszewski, Technical Report, (2009)

Early experience with a commercial hardware transactional memory implementation.
David Dice, Yossi Lev, Mark Moir, Daniel Nussbaum, ASPLOS

Early experience with a commercial hardware transactional memory implementation.
David Dice, Yossi Lev, Mark Moir, Daniel Nussbaum, ASPLOS 2009:157-168

Potential show-stoppers for transactional synchronization.
Ali-Reza Adl-Tabatabai, David Dice, Maurice Herlihy, Nir Shavit, Christos Kozyrakis, Christoph von Praun, Michael Scott, PPOPP 2007:55

Understanding Tradeoffs in Software Transactional Memory.
David Dice, Nir Shavit, CGO 2007:21-33

Transactional Locking II.
David Dice, Ori Shalev, Nir Shavit, DISC 2006:194-208

Supporting per-processor local-allocation buffers using lightweight user-level preemption notification.
Alex Garthwaite, David Dice, Derek White, VEE 2005:24-34

Supporting Per-processor Local-allocation Buffers Using Multi-processor Restartable Critical Sections
Derek White, David Dice, Alex Garthwaite, Technical Report, (2004)

Mostly lock-free malloc.
David Dice, Alex Garthwaite, MSP/ISMM 2002:269-280

Implementing Fast Java Monitors with Relaxed-Locks.
David Dice, Java Virtual Machine Research and Technology Symposium 2001:79-90

Implementing Fast Java™ Monitors with Relaxed-Locks.
David Dice, Java™ Virtual Machine Research and Technology Symposium 2001:79-90

Permuted Memory Access Mapping
(Jan 8, 2019)

Hardware Extensions For Memory Reclamation For Concurrent Data Structures
(Oct 10, 2017)

Transactional Execution Of Native Methods
(Aug 22, 2017)

System And Method For Implementing Shared Probabilistic Counters Storing Update Probability Values
(Aug 16, 2016)

System And Method For Implementing Reader-Writer Locks Using Hardware Transactional Memory
(May 17, 2016)

System And Method For Mitigating The Impact Of Branch Misprediction When Exiting Spin Loops
(Apr 5, 2016)

System And Method For Implementing Scalable Contention-Adaptive Statistics Counters
(Nov 10, 2015)

Systems And Methods For Adaptive Integration Of Hardware And Software Lock Elision Techniques
(Nov 10, 2015)

Partitioned Ticket Locks With Semi-Local Spinning
(Oct 13, 2015)

Supporting Targeted Stores In A Shared-Memory Multiprocessor System
(Aug 18, 2015)

Monitoring Multiple Memory Locations For Targeted Stores In A Shared-Memory Multiprocessor
(Mar 24, 2015)

System And Method For Implementing Numa-Aware Reader-Writer Locks
(Feb 24, 2015)

System And Method For Implementing Numa-Aware Statistics Counters
(Dec 23, 2014)

Method And System For Optimizing Code For A Multi-Threaded Application
(Sep 2, 2014)

System and method for reducing serialization in transactional memory using gang release of blocked threads
(Jul 22, 2014)

System And Method For Enabling Turbo Mode In A Processor
(Jul 8, 2014)

Method and system for hardware feedback in transactional memory
(Jul 8, 2014)

Systems And Methods For Detecting And Tolerating Atomicity Violations Between Concurrent Code Blocks
(May 20, 2014)

Page-protection based memory access barrier traps
(May 13, 2014)

Cache Index Coloring For Virtual-Address Dynamic Allocators
(Apr 22, 2014)

System And Method For Numa-Aware Locking Using Lock Cohorts
(Apr 8, 2014)

Multi-Lane Concurrent Bag For Facilitating Inter-Thread Communication
(Apr 1, 2014)

Lock-Clustering Compilation For Software Transactional Memory
(Mar 18, 2014)

System And Method For Tracking References To Shared Objects Using Byte-Addressable Per-Thread Reference Counters
(Mar 18, 2014)

System And Method For Performing Incremental Register Checkpointing In Transactional Memory
(Oct 15, 2013)

Concurrency Control Using Slotted Read-Write Locks
(Sep 17, 2013)

System And Method For Utilizing Available Best Effort Hardware Mechanisms For Supporting Transactional Memory
(Sep 10, 2013)

System And Method For Optimizing A Code Section By Forcing A Code Section To Be Executed Atomically
(Sep 10, 2013)

Method And System For Providing A Current Time Value
(Jun 25, 2013)

System And Method For Implementing Hierarchical Queue-Based Locks Using Flat Combining
(Jun 4, 2013)

Techniques for providing improved affinity scheduling in a multiprocessor computer system
(Mar 26, 2013)

System And Method For Managing Contention In Transactional Memory Using Global Execution Data
(Mar 19, 2013)

Fast And Efficient Reacquisition Of Locks For Transactional Memory Systems
(Feb 12, 2013)

Efficient Implicit Privatization Of Transactional Memory
(Dec 11, 2012)

Bulk Synchronization In Transactional Memory Systems
(Oct 30, 2012)

Advice-Based Feedback For Transactional Execution
(Oct 2, 2012)

Facilitating Transactional Execution Through Feedback About Misspeculation
(Jul 17, 2012)

System And Method For Transactional Locking Using Reader-Lists
(Jan 24, 2012)

System and method for transactional locking using reader-lists
(Jan 24, 2012)

Methods And Apparatus To Implement Parallel Transactions
(Nov 22, 2011)

Techniques For Providing Improved Affinity Scheduling In A Multiprocessor Computer System
(Nov 1, 2011)

Adaptive Spin-Then-Block Mutual Exclusion In Multi-Threaded Processing
(Oct 25, 2011)

Globally Incremented Variable Or Clock Based Methods And Apparatus To Implement Parallel Transactions
(Sep 27, 2011)

Optimistic Semi-Static Transactional Memory Implementations
(Mar 8, 2011)

Method And Apparatus For Switching Between Per-Thread And Per-Processor Resource Pools In Multi-Threaded Programs
(Feb 1, 2011)

Methods And Apparatus Providing Non-Blocking Access To A Resource
(Nov 30, 2010)

Quickly Reacquirable Locks
(Oct 12, 2010)

Fine-Locked Transactional Memory
(Sep 7, 2010)

Method Of Mixed Lock-Free And Locking Synchronization
(Jun 29, 2010)

Method And Apparatus For Executing A Long Transaction
(Feb 23, 2010)

Methods And Apparatus To Implement Parallel Transactions
(Feb 23, 2010)

Techniques For Accessing A Shared Resource Using An Improved Synchronization Mechanism
(Jan 5, 2010)

Methods and apparatus to implement parallel transactions
(Dec 29, 2009)

Adaptive Spin-Then-Block Mutual Exclusion In Multi-Threaded Processing
(Sep 22, 2009)

System And Methods For Deadlock Detection
(Feb 24, 2009)

Methods And Apparatus To Implement Parallel Transactions
(Feb 24, 2009)

Methods And Apparatus For Providing A Remote Serialization Guarantee
(Jan 6, 2009)

Methods And Apparatus For Selecting Processes For Execution
(Jan 8, 2008)

System And Method For Maintaining Data Synchronization
(Apr 3, 2007)

Methods And Apparatus For Executing Code While Avoiding Interference
(Feb 13, 2007)

Methods And Apparatus For Creating And Transforming Graphical Constructs
(Apr 4, 2006)

Multi-Threaded Garbage Collector Employing Cascaded Memory Arrays Of Task Identifiers To Implement Work Stealing Queues For Task Identification And Processing
(Mar 21, 2006)

Methods And Apparatus For Controlling Speculative Execution Of Instructions Based On A Multiaccess Memory Condition
(Apr 5, 2005)

Methods And Apparatus For Performing A Memory Management Technique
(Mar 1, 2005)

Speculative Execution Control With Programmable Indicator And Deactivation Of Multiaccess Recovery Mechanism
(Feb 8, 2005)

Methods And Apparatus For Executing Code While Avoiding Interference
(Sep 28, 2004)

Relaxed lock protocol
(May 11, 2004)

Mutual exculsion system and method for restarting critical sections of code when preempted during a critical section
(Feb 24, 2004)

System And Method Providing An Arrangement For Efficiently Emulating An Operating System Call
(Mar 4, 2003)

System And Method For Automatically And Selectively Promoting Object Variables To Method Fields And Variables In A Digital Computer System
(Oct 23, 2001)

System And Method For Efficiently Implementing An Authenticated Communications Channel That Facilitates Tamper Detection
(Sep 11, 2001)

System And Method For Synchronizing Access To Shared Variables In A Virtual Machine In A Digital Computer System
(Oct 31, 2000)

System and method for processing load instruction in accordance with "no-fault" processing facility including arrangement for preserving access fault indicia
(May 11, 1999)

Emulating a delayed exception on a digital computer having a corresponding precise exception mechanism
(Jul 7, 1998)

System and method for emulating a segmented virtual address space by a microprocessor that provides a non-segmented virtual address space
(Jun 9, 1998)

System and method for processing load instruction in accordance with "no-fault " processing facility including arrangement for preserving access fault indicia
(Jan 27, 1998)